Chip-area-efficient pattern and method of hierarchal power routing

ABSTRACT

A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks. Distribution electrodes for both the power supply voltage and reference voltage are located in both the first wiring layer and the second wiring layer and distribute the power supply voltage and reference voltage to each of the sub-blocks. Vias are used to connect distribution electrodes on one level to the same voltage distribution electrodes on the other level and to either the main bus for the power supply or the main bus for the reference voltage.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a method and pattern for routing powerand ground for an integrated circuit chip.

[0003] 2. Description of the Related Art

[0004] Distribution of a power supply voltage and a reference voltage toan integrated circuit chip is a key part of the chip wiring layoutdesign. Voltages must be distributed to all parts of the chip withinstrict voltage drop tolerances. Capacitance between the electrodessupplying the power and reference voltages can also be an importantconsideration.

[0005] U.S. Pat. No. 6,025,616 to Nguyen et al. describes a powerdistribution system for a semiconductor die which includes bonding padslocated adjacent to and connected to power busses with connections tothe bonding pads providing a parallel path for current.

[0006] U.S. Pat. No. 5,949,098 to Mori describes a semiconductorintegrated circuit having a power wiring layer and a ground wiring layerwith an insulating layer between the power and ground layers.

[0007] U.S. Pat. No. 5,313,079 to Brasen et al. describes gate arrayshaving functional blocks with flexible power routing.

[0008] U.S. Pat. No. 5,517,042 to Kitamura describes a semiconductordevice having first and second device regions, a first power supplyregion, and a second power supply region.

SUMMARY OF THE INVENTION

[0009] With large chips and dense circuitry becoming common it isimportant to provide power and ground routing which will make veryefficient use of chip area, reduce voltage drops due to electroderesistance, and provide decoupling capacitance between the power andground supply electrodes.

[0010] Currently the general practice in routing the top level power andground is to form the power and ground electrodes from the same metallayer. While more than one metal layers may be used to distribute powerand ground, each metal layer has both power and ground electrodes. Thisconventional arrangement is shown in FIGS. 1-3. FIG. 1 shows a compositetop view of a chip 10 having a circuit region 29 partitioned into fiveseparate sub-blocks, sub-block A 18, sub-block B 20, sub-block C 22,sub-block D 24, and sub-block E 26. The chip 10 has a peripheral region12 for input output tabs, not shown. The chip has a power bus 14 and aground bus 16. FIG. 1 is a composite top surface view showing the wiringfor two separate metal layers. The electrodes in the horizontaldirection are in one metal layer and the electrodes in the verticaldirection are in another wiring layer. The inter layer contacts for thepower bus 14 are shown as darkened regions 28. The inter layer contactsfor the ground bus are also shown as darkened regions 30.

[0011]FIG. 2 shows the metal layer having the power bus electrodes 14Hand the ground bus electrodes 16H in the horizontal direction. FIG. 3shows the metal layer having the power bus electrodes 14V and the groundbus electrodes 16V in the vertical direction.

[0012] This arrangement results in power and ground routed in parallelelectrodes in the same metal which restricts the width of the power andground busses and provides very little decoupling capacitance betweenthe power and ground electrodes. For large chips and dense circuitry thecurrent practice results in significant voltage drop due to theresistance of long power and ground electrodes and insufficientdecoupling capacitance between power and ground electrodes.

[0013] It is a principle objective of this invention to provide a methodof routing power and ground wiring which makes efficient use of chiparea, reduces voltage drops due to electrode resistance, and providesincreased decoupling capacitance between power and ground electrodes.

[0014] It is another principle objective of this invention to provide apower and ground wiring layout which makes efficient use of chip area,reduces voltage drops due to electrode resistance, and providesincreased decoupling capacitance between power and ground electrodes.

[0015] These objectives are achieved by using the two top wiring layersas power distribution layers to distribute the power supply voltage,such as V_(DD), and reference voltage, such as ground or V_(SS), so thepower supply voltage bus electrode and the reference voltage buselectrode are on separate wiring levels. The power supply voltage buselectrode and the reference voltage bus electrode are in adjacent wiringlayers and in the same location on the chip so that decouplingcapacitance between the power supply voltage bus electrode and referencevoltage bus electrode is maximized. Since the power supply voltage buselectrode and the reference voltage bus electrode are in separate wiringlayers the width of these electrodes can be maximized to reduce thevoltage drop due to the resistance of the electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 shows a composite top view of a chip having a conventionalpower and ground distribution system.

[0017]FIG. 2 shows a top view of the wiring level having electroderouting in the horizontal direction for a chip having a conventionalpower and ground distribution system.

[0018]FIG. 3 shows a top view of the wiring level having electroderouting in the vertical direction for a chip having a conventional powerand ground distribution system.

[0019]FIG. 4A shows a top view of the first power bus electrodes in thefirst power wiring layer for a chip having the power and ground wiringlayout of this invention.

[0020]FIG. 4B shows a top view of the second power bus electrodes in thesecond power wiring layer for a chip having the power and ground wiringlayout of this invention.

[0021]FIG. 5A shows a top view of the distribution electrodes in thefirst power wiring layer for a chip having the power and ground wiringlayout of this invention.

[0022]FIG. 5B shows a top view of the distribution electrodes in thesecond power wiring layer for a chip having the power and ground wiringlayout of this invention.

[0023]FIG. 6A shows a three dimensional view of the first and secondpower bus electrodes in the first and second power wiring layers for achip having the power and ground wiring layout of this invention.

[0024]FIG. 6B shows a three dimensional view of the distributionelectrodes in the first and second power wiring layers for a chip havingthe power and ground wiring layout of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Refer now to FIGS. 4A-6B for a description of the preferredembodiments of this invention. This invention relates to thedistribution of the power supply voltage, such as V_(DD), and thereference voltage, ground or V_(SS), in an integrated circuit chip. Thisinvention applies to any integrated circuit chip, but is particularlyuseful for those chips having five or more wiring layers. A key elementof this invention is that the power supply voltage, or V_(DD), buselectrode is located in a single wiring layer and the reference voltage,ground or V_(SS), bus electrode is also located in a single and separatewiring layer.

[0026] In this invention, as shown in FIGS. 4A, 4B, and 6A, the chip isfirst partitioned into a number of sub-blocks with wiring space betweenthe sub-blocks. In this example the circuit region 29 of the chip ispartitioned into sub-block A 18, sub-block B 20, sub-block C 22,sub-block D 24, and sub-block E 26. As shown in FIGS. 4A, 4B, and 6Athere are wiring spaces between the sub-blocks. Also shown in FIGS. 4Aand 4B there is a space 12 around the periphery of the circuit region 29of the chip for input output pads, not shown. Although five sub-blocksare shown in this example those skilled in the art will readilyrecognize that a larger or smaller number of sub-blocks could be used.

[0027]FIGS. 4A and 4B show the top views of the main electrodes used todistribute the power supply voltage, or V_(DD), and the referencevoltage, ground or V_(SS). In this example FIG. 4A shows the powersupply voltage bus electrode 42 and FIG. 4B shows the reference voltagebus electrode 44. The power supply voltage bus electrode 42, FIG. 4A,and the reference voltage bus electrode 44, FIG. 4B, are in separatewiring layers. In this example the wiring layer having the power supplyvoltage bus 42, shown in FIG. 4A, will be referred to as the firstwiring layer and the wiring layer having the reference voltage bus 44,shown in FIG. 4B, will be referred to as the second wiring layerTypically the first wiring layer and the second wiring layer areadjacent wiring layers. As shown in FIG. 4A the power supply voltage buselectrode 42 is routed around each of the sub-blocks and in each of thespaces between the sub-blocks. The power supply voltage bus electrode 42is shown cross hatched in FIG. 4A to improve the clarity of the drawing.As shown in FIG. 4B the reference voltage bus electrode 44 is routedaround each of the sub-blocks and in each of the spaces between thesub-blocks. The reference voltage bus electrode 44 is shown shaded inFIG. 4B to improve the clarity of the drawing.

[0028] The power supply voltage bus electrode 42, shown in FIG. 4A, andthe reference voltage bus electrode 44, shown in FIG. 4B, have the samesize, shape, and location within their wiring layer so that one islocated directly above the other in adjacent wiring levels. Thismaximizes the decoupling capacitance between the power supply voltagebus electrode 42 and the reference voltage bus electrode 44. Since thepower supply voltage bus electrode 42 and the reference voltage buselectrode 44 are each located on a separate wiring layer the width ofthese electrodes can be maximized thereby minimizing the voltage dropdue to resistance of these electrodes. Those skilled in the art willreadily recognize that either the power supply voltage bus electrode 42can be located above the reference voltage bus electrode 44, or thereference voltage bus electrode 44 can be located above the power supplyvoltage bus electrode 42.

[0029]FIG. 5A shows the top view of the power supply voltagedistribution electrodes, 143H and 143V, and the reference voltagedistribution electrodes 145H in the first wiring layer used todistribute the power supply voltage, or V_(DD), and the referencevoltage, ground or V_(SS), into the sub-blocks. FIG. 5B shows the topview of the power supply voltage distribution electrodes 243V and thereference voltage distribution electrodes, 245V and 245H, in the secondwiring layer used to distribute the power supply voltage, or V_(DD), andthe reference voltage, ground or V_(SS), into the sub-blocks. While thepower supply voltage bus electrodes and the reference voltage buselectrodes are in separate wiring layers, there are both power supplyvoltage distribution electrodes and reference voltage distributionelectrodes in both the first wiring layer and the second wiring layer.In FIGS. 5A and 5B sub-block A 18 is used as a representative example.Those skilled in the art will readily recognize that the power supplyvoltage, or V_(DD), and the reference voltage, ground or V_(SS), will bedistributed to the remaining sub-blocks in like manner.

[0030]FIG. 5A shows the power supply voltage distribution electrodes,143H and 143V, and reference voltage distribution electrodes 145H in thefirst wiring layer. FIG. 5B shows the power supply voltage distributionelectrodes 243V and reference voltage distribution electrodes, 245V and245H, in the second wiring layer. As shown in FIGS. 5A and 5B, firstvias 50 are used to connect the power supply voltage bus 42 and thepower supply voltage distribution electrodes, 143H and 143V, on thefirst wiring layer to the power supply voltage distribution electrodes243V on the second wiring layer. Also as shown in FIGS. 5A and 5B,second vias 52 are used to connect the reference voltage bus 44 and thereference voltage distribution electrodes, 245H and 245V, on the secondwiring layer to the reference voltage distribution electrodes 145H onthe first wiring layer.

[0031] Refer to FIGS. 6A and 6B for a further description of theelectrode routing in the first wiring layer and the second wiring layer.FIG. 6A shows a three dimensional view of the first and second wiringlayers. FIG. 6A shows the power supply voltage bus electrode 42 locateddirectly over the reference voltage bus electrode 44. In FIG. 6A thepower supply voltage bus electrode 42 is shown cross-hatched and thereference voltage bus electrode 44 is shown shaded to aid in the clarityof the drawing. FIG. 6B shows the detail of the distribution intosub-block A 18 and sub-block B 20 for the region 54 identified by thedashed line.

[0032] In FIG. 6B the electrodes on the first wiring level are showncross-hatched and the electrodes on the second wiring level are shownwithout cross-hatching or shading. As shown in FIG. 6B the referencevoltage bus electrode 44 on the second wiring layer is connected toreference voltage distribution electrodes 145H on the first wiring layerthrough second vias 52. Also as shown in FIG. 6B the power supplyvoltage bus electrode 42 on the first wiring layer is connected to powersupply voltage distribution electrodes 243H on the second wiring layerthrough first vias 50. Also as shown in FIG. 6B, the power supplyvoltage distribution electrodes 143H on the first wiring layer areconnected to the power supply distribution electrodes 243V on the secondwiring layer through first vias 50, and the reference voltagedistribution electrodes 243V on the second wiring layer are connected tothe reference voltage distribution electrodes 143H on the first wiringlayer through second vias 52.

[0033]FIGS. 5A, 5B, and 6B show the power supply voltage distributionelectrodes and reference voltage distribution electrodes on the firstwiring layer oriented horizontally, and the power supply voltagedistribution electrodes and reference voltage distribution electrodes onthe second wiring layer oriented vertically. Those skilled in the artwill readily recognize that the invention will work equally well if thepower supply voltage distribution electrodes and reference voltagedistribution electrodes on the first wiring layer were orientedvertically, and the power supply voltage distribution electrodes andreference voltage distribution electrodes on the second wiring layerwere oriented horizontally.

[0034] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of routing power and ground forintegrated circuit chips, comprising: providing an integrated circuitchip, wherein said integrated circuit chip has a circuit region;partitioning said circuit region of said integrated circuit chip into anumber of sub-block regions having spaces therebetween; providing afirst power wiring layer and a second power wiring layer; providingfirst vias between said first power wiring layer and said second powerwiring layer; providing second vias between said first power wiringlayer and said second power wiring layer; forming a first power buselectrode in said first power wiring layer wherein said first power buselectrode surrounds said circuit region and each of said sub-blockregions; forming a second power bus electrode in said second powerwiring layer wherein said second power bus electrode is directly undersaid first power bus electrode, surrounds said circuit region, andsurrounds each of said sub-block regions; forming first distributionelectrodes in said first power wiring layer electrically connected tosaid first power bus electrode wherein said first distributionelectrodes supply the voltage on said first power bus electrode to eachof said sub-block regions; forming second distribution electrodes insaid second power wiring layer electrically connected to said firstpower bus electrode and said first distribution electrodes by means ofsaid first vias wherein said second distribution electrodes supply thevoltage on said first power bus electrode to each of said sub-blockregions; forming third distribution electrodes in said second powerwiring layer electrically connected to said second power bus electrodewherein said third distribution electrodes supply the voltage on saidsecond power bus electrode to each of said sub-block regions; andforming fourth distribution electrodes in said first power wiring layerelectrically connected to said second power bus electrode and said thirddistribution electrodes by means of said second vias wherein said fourthdistribution electrodes supply the voltage on said second power buselectrode to each of said sub-block regions.
 2. The method of claim 1further comprising a number of signal wiring layers.
 3. The method ofclaim 2 wherein said number of signal wiring layers is at least fivesignal wiring layers.
 4. The method of claim 1 wherein said first powerwiring layer and said second wiring layer are adjacent wiring layers. 5.The method of claim 1 wherein said first power bus electrode isconnected to a voltage supply and said second power bus electrode isconnected to electrical ground.
 6. The method of claim 1 wherein saidfirst power bus electrode is connected to a V_(DD) voltage supply andsaid second power bus electrode is connected to a V_(SS) voltage supply.7. The method of claim 1 wherein said number of sub-blocks is five.
 8. Amethod of routing power and ground for integrated circuit chips,comprising: providing an integrated circuit chip, wherein saidintegrated circuit chip has devices formed therein, a circuit region,and a plurality of signal wiring layers; partitioning said circuitregion of said integrated circuit chip into a number of sub-blockregions having spaces therebetween; forming a first cap dielectric layeron said integrated circuit chip thereby covering said signal wiringlayers; forming a first power bus electrode on said first cap dielectriclayer wherein said first power bus electrode surrounds said circuitregion and each of said sub-block regions; forming first distributionelectrodes on said first cap dielectric layer electrically connected tosaid first power bus electrode wherein said first distributionelectrodes supply the voltage on said first power bus electrode to eachof said sub-block regions; forming second distribution electrodes onsaid first cap dielectric layer; forming a second cap dielectric layeron said integrated circuit chip thereby covering said first power buselectrode, said first distribution electrodes, and said seconddistribution electrodes; providing first vias through said second capdielectric layer; providing second vias through said second capdielectric layer; forming a second power bus electrode on said secondcap dielectric layer wherein said second power bus electrode is directlyover said first power bus electrode, surrounds said circuit region,surrounds each of said sub-block regions, and is connected to saidsecond distribution electrodes by means of said second vias, wherebysaid second distribution electrodes supply the voltage on said secondpower bus electrode to each of said sub-block regions; forming thirddistribution electrodes on said second cap dielectric layer electricallyconnected to said second power bus electrode and to said seconddistribution electrodes by means of said second vias, wherein said thirddistribution electrodes supply the voltage on said second power buselectrode to each of said sub-block regions; and forming fourthdistribution electrodes on said second cap dielectric layer electricallyconnected to said first power bus electrode and said first distributionelectrodes by means of said first vias, wherein said fourth distributionelectrodes supply the voltage on said first power bus electrode to eachof said sub-block regions.
 9. The method of claim 8 wherein said firstnumber is five or greater.
 10. The method of claim 8 wherein said firstpower bus electrode is connected to a voltage supply and said secondpower bus electrode is connected to electrical ground.
 11. The method ofclaim 8 wherein said first power bus electrode is connected to a V_(DD)voltage supply and said second power bus electrode is connected to aV_(SS) voltage supply.
 12. The method of claim 8 wherein said secondnumber is five.
 13. A power and ground routing pattern for an integratedcircuit chip, comprising: an integrated circuit chip, wherein saidintegrated circuit chip has devices formed therein, a first number ofsignal wiring layers, and a circuit region partitioned into a secondnumber of sub-block regions having spaces therebetween; a first capdielectric layer formed on said integrated circuit chip thereby coveringsaid first number of signal wiring layers; a first power wiring layerformed on said first cap dielectric layer; a second cap dielectric layerformed on said first power wiring layer; a second power wiring layerformed on said second cap dielectric layer; a plurality of first viasbetween said first power wiring layer and said second power wiringlayer; a plurality of second vias between said first power wiring layerand said second power wiring layer; a first power bus electrode formedin said first power wiring layer wherein said first power bus electrodesurrounds said circuit region and each of said sub-block regions; asecond power bus electrode formed in said second power wiring layerwherein said second power bus electrode is directly under said firstpower bus electrode, surrounds said circuit region, and surrounds eachof said sub-block regions; first distribution electrodes formed in saidfirst power wiring layer electrically connected to said first power buselectrode wherein said first distribution electrodes supply the voltageon said first power bus electrode to each of said sub-block regions;second distribution electrodes formed in said second power wiring layerelectrically connected to said first power bus electrode and said firstdistribution electrodes by means of said first vias wherein said seconddistribution electrodes supply the voltage on said first power buselectrode to each of said sub-block regions; third distributionelectrodes formed in said second power wiring layer electricallyconnected to said second power bus electrode wherein said thirddistribution electrodes supply the voltage on said second power buselectrode to each of said sub-block regions; and fourth distributionelectrodes formed in said first power wiring layer electricallyconnected to said second power bus electrode and said third distributionelectrodes by means of said second vias wherein said fourth distributionelectrodes supply the voltage on said second power bus electrode to eachof said sub-block regions.
 14. The power and ground routing pattern ofclaim 13 wherein said first number is five or greater.
 15. The power andground routing pattern of claim 13 wherein said first power buselectrode is connected to a voltage supply and said second power buselectrode is connected to electrical ground.
 16. The power and groundrouting pattern of claim 13 wherein said first power bus electrode isconnected to a V_(DD) voltage supply and said second power bus electrodeis connected to a V_(SS) voltage supply.
 17. The power and groundrouting pattern of claim 13 wherein said second number is five.